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exar corporation 48720 kato road, fremont ca, 94538 ? (50)668-70 7 ? www.exar.com sp3508_00_072208 features ? fast 20mbps differential transmission rates ? internal transceiver termination resistors for v. & v.35 ? interface modes: rs-232 (v.28) eia-530 (v. 0 & v. ) x.2 (v. ) eia-530a (v. 0 & v. ) rs-449/v.36 v.35 (v.35 & v.28) (v. 0 & v. ) ? protocols are software selectable with 3-bit word ? eight (8) drivers and eight (8) receivers ?termination network disable option ? internal line or digital loopback for diagnostic testing ? certifed conformance to net1/net2 and tbr-1 tbr-2 by tuv rheinland (tbr2/3045 940.00/04) ? easy flow-through pinout ? +3.3v only operation ? individual driver and receiver enable/disable controls ?operates in either dte or dce mode sp3508 rugged 3.3v, 20mbps, 8 channel multiprotocol transceiver with programmable dce/dte and termination resistors description the sp3508 is a monolithic device that supports eight (8) popular serial interface standards for wide area network (wan) connectivity. the sp3508 is fabricated using a low power bicmos process technology, and incorporates a regulated charge pump allowing +3.3v only operation. exar's patented charge pump provides a regulated output of + 5.5v, which will provide enough voltage for compliant operation in all modes. eight (8) drivers and eight (8) receivers can be confgured via software for any of the above interface modes at any time. the sp3508 requires no additional external components for compliant operation for all of the eight (8) modes of operation other than six capacitors used for the internal charge pump. all necessary termination is integrated within the sp3508 and is switchable when v.35 drivers and v.35 receivers, or when v. receivers are used. the sp3508 provides the controls and transceiver availability for operating as either a dte or dce. additional features with the sp3508 include internal loopback that can be initiated in any of the operating modes by use of the loopback pin. while in loopback mode, receiver outputs are internally connected to driver inputs creating an internal signal path bypassing the serial communications controller for diagnostic testing. the sp3508 also includes a latch enable pin with the driver and receiver address decoder. the internal v. or v.35 termination can be switched off using a control pin (term_off) for monitoring applications. all eight (8) drivers and receivers in the sp3508 include separate enable pins for added convenience. the sp3508 is ideal for wan serial ports in networking equipment such as routers, access concentrators, network muxes, dsu/csu's, networking test equipment, and other access devices. applications ? router ? frame relay ? csu ? dsu ? pbx ? secure communication terminals now available in lead free packaging refer to page 9 for pinout
2 exar corporation 48720 kato road, fremont ca, 94538 ? (50)668-70 7 ? www.exar.com sp3508_00_072208 electrical specifications t a = 0 to 70c and v cc = 3.3v 5% unless otherwise noted. the ? denotes the specifcations which apply over the full operating tempera - ture range (-40 c to +85 c) , unless otherwise specifed. v cc ................................................................................................. +7v input voltages: logic ................................................ -0.3v to (v cc +0.5v) drivers .............................................. -0.3v to (v cc +0.5v) receivers ............................................................. 5.5v output voltages: logic ................................................ -0.3v to (v cc +0.5v) drivers ..................................................................... 2v receivers ......................................... -0.3v to (v cc +0.5v) storage temperature .................................................. -65 c to +50c power dissipation ................................................................... 520mw (derate 9.0mw/ c above +70 c) junction temperature t j ......................................................... +4c due to the relatively large package size of the 00-pin quad fat-pack, storage in a low humidity environment is preferred. large high density plastic packages are moisture sensitive and should be stored in dry vapor barrier bags. prior to usage, the parts should remain bagged and stored below 40c and 60%rh. if the parts are removed from the bag, they should be package derating: ? ja ................................................................... 36.9 c/w ? jc ..................................................................... 6.5 c/w these are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifcations below is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. absolute maximum ratings used within 48 hours or stored in an environment at or below 20%rh. if the above conditions cannot be followed, the parts should be baked for four hours at 25c in order to remove moisture prior to soldering. exar ships the 00-pin lqfp in dry vapor barrier bags with a humidity indicator card and desiccant pack. the humidity indicator should be below 30%rh. storage considerations parameter min. typ. max. units conditions logic inputs v il 0.8 ? v v ih 2.0 ? v logic outputs v ol 0.4 ? v i out = -3.2ma v oh v cc - 0.6 v cc - 0.3 ? v i out = .0ma v.28 driver dc parameters (outputs) open circuit voltage +/-0 ? v per figure loaded voltage +/-5.0 ? v per figure 2 short-circuit current +/-00 ? ma per figure 4 power-off impedance 300 ? ? per figure 5 v.28 driver ac parameters (outputs) v cc = 3.3v for ac parameters transition time .5 ? s per figure 6, +3v to -3v instantaneous slew rate 30 v/ s per figure 3 propagation delay: t phl 0.5 .0 3.0 ? s propagation delay: t plh 0.5 .0 3.0 ? s max. transmission rate 20 230 ? kbps
3 exar corporation 48720 kato road, fremont ca, 94538 ? (50)668-70 7 ? www.exar.com sp3508_00_072208 electrical specifications t a = 0 to 70c and v cc = 3.3v 5% unless otherwise noted. the ? denotes the specifcations which apply over the full operating tempera - ture range (-40 c to +85 c) , unless otherwise specifed. parameter min. typ. max. units conditions v.28 receiver dc parameters (inputs) input impedance 3 7 ? k? per figure 7 open-circuit bias +2.0 ? v per figure 8 high threshold .7 3.0 ? v low threshold 0.8 .2 ? v v.28 receiver ac parameters v cc = 3.3v for ac parameters propagation delay: t phl 00 500 ns propagation delay: t plh 00 500 ns max. transmission rate 20 230 kbps v.10 driver dc parameters (outputs) open circuit voltage +/-4.0 +/-6.0 ? v per figure 9 test-terminated voltage 0.9v cc v per figure 0 short-circuit current +/-50 ma per figure power-off current +/-00 ? a per figure 2 v.10 driver ac parameters (outputs) v cc = 3.3v for ac parameters transition time 200 ? ns per figure 3, 0% to 90% propagation delay: t phl 00 500 ? ns propagation delay: t plh 00 500 ? ns max. transmission rate 20 ? kbps v.10 receiver dc parameters (inputs) input current -3.25 +3.25 ma per figures 4 and 5 input impedance 4 ? k? sensitivity +/-0.3 ? v v.10 receiver ac parameters v cc = 3.3v for ac parameters propagation delay: t phl 20 250 ? ns propagation delay: t plh 20 250 ? ns max. transmission rate 20 ? kbps
4 exar corporation 48720 kato road, fremont ca, 94538 ? (50)668-70 7 ? www.exar.com sp3508_00_072208 electrical specifications t a = 0 to 70c and v cc = 3.3v 5% unless otherwise noted. the ? denotes the specifcations which apply over the full operating tempera - ture range (-40 c to +85 c) , unless otherwise specifed. parameter min. typ. max. units conditions v.11 driver dc parameters (outputs) open circuit voltage (v oc ) +/-6.0 ? v per figure 6 test terminated voltage +/-2.0 ? v per figure 7 0.5(v oc ) ? v balance +/-0.4 v per figure 7 offset +3.0 ? v per figure 7 short-circuit current +/-50 ? ma per figure 8 power-off current +/-00 ? a per figure 9 v.11 driver ac parameters (outputs) v cc = 3.3v for ac parameters transition time 0 ? ns per figures 2 and 35, 0% to 90% using c l = 50pf propagation delay: t phl 30 85 ? ns per figures 32 and 35 propagation delay: t plh 30 85 ? ns per figures 32 and 35 differential skew 5 0 ? ns per figures 32 and 35 max. transmission rate 20 ? mbps v.11 receiver dc parameters (inputs) common mode range -7 +7 ? v sensitivity +/-0.2 ? v input current -3.25 +3.25 ma per figures 20 and 22; power on or off current with 100? termination +/-60 ma per figures 23 and 24 input impedance 4 ? k? v.11 receiver ac parameters v cc = 3.3v for ac parameters us - ing cl = 50pf propagation delay: t phl 30 85 ns per figures 32 and 37 propagation delay: t plh 30 85 ns per figures 32 and 37 skew 5 0 ns per figure 32 max. transmission rate 20 mbps
5 exar corporation 48720 kato road, fremont ca, 94538 ? (50)668-70 7 ? www.exar.com sp3508_00_072208 electrical specifications t a = 0 to 70c and v cc = 3.3v 5% unless otherwise noted. the ? denotes the specifcations which apply over the full operating tempera - ture range (-40 c to +85 c) , unless otherwise specifed. parameter min. typ. max. units conditions v.35 driver dc parameters (outputs) open circuit voltage +/-.20 v per figure 6 test terminated voltage +/-0.44 +/-0.66 v per figure 25 offset +/-0.6 ? v per figure 25 output overshoot -0.2v st +0.2v st ? v per figure 25; v st = steady state value source impedance 50 50 ? ? per figure 26; z s = v 2 /v x 50 short-circuit impedance 35 65 ? per figure 27 v.35 driver ac parameters (outputs) v cc = 3.3v for ac parameters transition time 20 ? ns propagation delay: t phl 30 85 ? ns per figures 32 and 35; c l = 20pf propagation delay: t plh 30 85 ? ns per figures 32 and 35; c l = 20pf differential skew 5 ? ns per figures 32 and 35; c l = 20pf max. transmission rate 20 ? mbps v.35 receiver dc parameters (inputs) sensitivity +/-50 +/-200 ? mv source impedance 90 0 ? per figure 29; z s = v 2 /v x 50? short-circuit impedance 35 65 ? per figure 30 v.35 receiver ac parameters v cc = 3.3v for ac parameters propagation delay: t phl 30 85 ns per figures 32 and 37; c l = 20pf propagation delay: t plh 30 85 ns per figures 32 and 37; c l = 20pf skew 5 0 ns per figure 32; c l = 20pf max. transmission rate 20 mbps transceiver leakage currents driver output 3-state cur - rent 200 a per figure 3; drivers disabled receiver output 3-state current 0 a d x =
6 exar corporation 48720 kato road, fremont ca, 94538 ? (50)668-70 7 ? www.exar.com sp3508_00_072208 electrical specifications t a = 0 to 70c and v cc = 3.3v 5% unless otherwise noted. the ? denotes the specifcations which apply over the full operating tempera - ture range (-40 c to +85 c) , unless otherwise specifed. parameter min. typ. max. units conditions power requirements v cc 3.5 3.3 3.45 v i cc (no mode selected) ? a all i cc values are with v cc = +3.3v (v.28 / rs-232) 95 ? ma f in = 230kbps; drivers active and loaded (v. / rs-422) 230 ? ma f in = 20mbps; drivers active and loaded (eia-530 & rs-449) 270 ? ma f in = 20mbps; drivers active and loaded (v.35) 70 ? ma v.35 @ f in = 20mbps, v.28 @ f in = 230kbps
7 exar corporation 48720 kato road, fremont ca, 94538 ? (50)668-70 7 ? www.exar.com sp3508_00_072208 other ac characteristics parameter min. typ. max. units conditions driver delay time between active mode and tri-state mode rs-232/v.28 t pzl ; tri-state to output low 0.70 5.0 s c l = 00pf, fig. 33 & 39 ; s closed t pzh ; tri-state to output high 0.40 2.0 s c l = 00pf, fig. 33 & 39 ; s 2 closed t plz ; output low to tri-state 0.20 2.0 s c l = 00pf, fig. 33 & 39 ; s closed t phz ; output high to tri-state 0.40 2.0 s c l = 00pf, fig. 33 & 39 ; s 2 closed rs-423/v.10 t pzl ; tri-state to output low 0.5 2.0 s c l = 00pf, fig. 33 & 39 ; s closed t pzh ; tri-state to output high 0.20 2.0 s c l = 00pf, fig. 33 & 39 ; s 2 closed t plz ; output low to tri-state 0.20 2.0 s c l = 00pf, fig. 33 & 39 ; s closed t phz ; output high to tri-state 0.5 2.0 s c l = 00pf, fig. 33 & 39 ; s 2 closed rs-422/v.11 t pzl ; tri-state to output low 2.80 0.0 s c l = 00pf, fig. 33 & 36 ; s closed t pzh ; tri-state to output high 0.0 2.0 s c l = 00pf, fig. 33 & 36 ; s 2 closed t plz ; output low to tri-state 0.0 2.0 s c l = 5pf, fig. 33 & 36 ; s closed t phz ; output high to tri-state 0.0 2.0 s c l = 5pf, fig. 33 & 36 ; s 2 closed v.35 t pzl ; tri-state to output low 2.60 0.0 s c l = 00pf, fig. 33 & 36 ; s closed t pzh ; tri-state to output high 0.0 2.0 s c l = 00pf, fig. 33 & 36 ; s 2 closed t plz ; output low to tri-state 0.0 2.0 s c l = 5pf, fig. 33 & 36 ; s closed t phz ; output high to tri-state 0.5 2.0 s c l = 5pf, fig. 33 & 36 ; s 2 closed receiver delay time between active mode and tri-state mode rs-232/v.28 t pzl ; tri-state to output low 0.2 2.0 s c l = 00pf, fig. 34 & 37 ; s closed t pzh ; tri-state to output high 0.0 2.0 s c l = 00pf, fig. 34 & 37 ; s 2 closed t plz ; output low to tri-state 0.0 2.0 s c l = 00pf, fig. 34 & 37 ; s closed t phz ; output high to tri-state 0.0 2.0 s c l = 00pf, fig. 34 & 37 ; s 2 closed rs-423/v.10 t pzl ; tri-state to output low 0.0 2.0 s c l = 00pf, fig. 34 & 37 ; s closed t pzh ; tri-state to output high 0.0 2.0 s c l = 00pf, fig. 34 & 37 ; s 2 closed t plz ; output low to tri-state 0.0 2.0 s c l = 00pf, fig. 34 & 37 ; s closed t phz ; output high to tri-state 0.0 2.0 s c l = 00pf, fig. 34 & 37 ; s 2 closed t a = 0 to 70c and v cc = 3.3v 5% unless otherwise noted.
8 exar corporation 48720 kato road, fremont ca, 94538 ? (50)668-70 7 ? www.exar.com sp3508_00_072208 other ac characteristics: c ontinued t a = 0 to 70c and v cc = +3.3v unless otherwise noted. parameter min. typ. max. units conditions rs-422/v.11 t pzl ; tri-state to output low 0.0 2.0 s c l = 00pf, fig. 34 & 38 ; s closed t pzh ; tri-state to output high 0.0 2.0 s c l = 00pf, fig. 34 & 38 ; s 2 closed t plz ; output low to tri-state 0.0 2.0 s c l = 5pf, fig. 34 & 38 ; s closed t phz ; output high to tri-state 0.0 2.0 s c l = 5pf, fig. 34 & 38 ; s 2 closed v.35 t pzl ; tri-state to output low 0.0 2.0 s c l = 00pf, fig. 34 & 38 ; s closed t pzh ; tri-state to output high 0.0 2.0 s c l = 00pf, fig. 34 & 38 ; s 2 closed t plz ; output low to tri-state 0.0 2.0 s c l = 5pf, fig. 34 & 38 ; s closed t phz ; output high to tri-state 0.0 2.0 s c l = 5pf, fig. 34 & 38 ; s 2 closed transceiver to transceiver s kew (per figures 32, 35, 37) rs-232 driver 00 ns [ (t phl )tx C (t phl )txn ] 00 ns [ (t plh )tx C (t plh )txn] rs-232 receiver 20 ns [ (t phl )rx C (t phl )rxn ] 20 ns [ (t plh )rx C (t plh )rxn ] rs-422 driver 2 ns [ (t phl )tx C (t phl )txn ] 2 ns [ (t plh )tx C (t plh )txn ] rs-422 receiver 3 ns [ (t phl )rx C (t phl: )rxn ] 3 ns [ (t plh )rx C (t plh )rxn ] rs-423 driver 5 ns [ (t phl )tx2 C (t phl )txn ] 5 ns [ (t plh )tx2 C (t plh )txn ] rs-423 receiver 5 ns [ (t phl )rx2 C (t phl )rxn ] 5 ns [ (t plh )rx2 C (t plh )rxn ] v.35 driver 4 ns [ (t phl )tx C (t phl )txn ] 4 ns [ (t plh )tx C (t plh )txn ] v.35 receiver 6 ns [ (t phl )rx C (t phl )rxn ] 6 ns [ (t plh )rx C (t plh )rxn]
9 exar corporation 48720 kato road, fremont ca, 94538 ? (50)668-70 7 ? www.exar.com sp3508_00_072208 pinout
0 exar corporation 48720 kato road, fremont ca, 94538 ? (50)668-70 7 ? www.exar.com sp3508_00_072208 sp3508 pin designation pin number pin name description gnd signal ground 2 sden txd driver enable input 3 tten txce driver enable input 4 sten st driver enabe input 5 rsen rts driver enable input 6 tren dtr driver enable input 7 rrcen dcd driver enable input 8 rlen rl driver enable input 9 llen# ll driver enable input 0 rden# rxd receiver enabe input rten# rxc receiver enable input 2 txcen# txc receiver enable input 3 csen# cts receiver enable input 4 dmen# dsr receiver enable input 5 rrten# dcd dte receiver enable input 6 icen# ri receiver enable input 7 tmen tm receiver enable input 8 d0 mode select input 9 d mode select input 20 d2 mode select input 2 dlatch# decoder latch input 22 term_off termination disable input 23 vcc power supply input 24 c3p charge pump capacitor 25 gnd signal ground
exar corporation 48720 kato road, fremont ca, 94538 ? (50)668-70 7 ? www.exar.com sp3508_00_072208 sp3508 pin designation pin number pin name description 26 c3n charge pump capacitor 27 vss2 minus vcc 28 agnd signal ground 29 avcc power supply input 30 loopback# loopback mode enable input 3 txd txd driver ttl input 32 txce txce driver ttl input 33 st st driver ttl input 34 rts rts driver ttl input 35 dtr dtr driver ttl input 36 dcd_dce dcd dce driver ttl input 37 rl rl driver ttl input 38 ll ll driver ttl input 39 rxd rxd receiver ttl output 40 rxc rxc receiver ttl output 4 txc txc receiver ttl output 42 cts cts receiver ttl output 43 dsr dsr receiver ttl output 44 dcd_dte dcd dte receiver ttl output 45 ri ri receiver ttl output 46 tm tm receiver ttl output 47 gnd signal ground 48 vcc power supply input 49 rd(b) rxd non-inverting input 50 rd(a) rxd inverting input
2 exar corporation 48720 kato road, fremont ca, 94538 ? (50)668-70 7 ? www.exar.com sp3508_00_072208 sp3508 pin designation pin number pin name description 5 rt(b) rxc non-inverting input 52 rt(a) rxc inverting input 53 txc(b) txc non-inverting input 54 gnd signal ground 55 txc(a) txc inverting input 56 cs(b) cts non-inverting input 57 cs(a) cts inverting input 58 dm(b) dsr non-inverting input 59 dm(a) dsr inverting input 60 gndv0 v. 0 rx reference node 6 rrt(b) dcd dte non-inverting input 62 rrt(a) dcd dte inverting input 63 ic ri receiver input 64 tm(a) tm receiver input 65 ll(a) ll driver output 66 vcc power supply input 67 rl(a) rl driver output 68 vss -2xvcc charge pump output 69 c2n charge pump capacitor 70 cn charge pump capacitor 7 gnd signal ground 72 c2p charge pump capacitor 73 vcc power supply input 74 cp charge pump capacitor 75 gnd signal ground
3 exar corporation 48720 kato road, fremont ca, 94538 ? (50)668-70 7 ? www.exar.com sp3508_00_072208 sp3508 pin designation pin number pin name description 76 vdd 2xvcc charge pump output 77 rrc(b) dcd dce non-inverting output 78 vcc power supply input 79 rrc(a) dcd dce inverting output 80 gnd signal ground 8 rs(a) rts inverting output 82 vcc power supply input 83 rs(b) rts non-inverting output 84 gnd signal ground 85 tr(a) dtr inverting output 86 vcc power supply input 87 tr(b) dtr non-inverting output 88 gnd signal ground 89 st(a) st inverting output 90 vcc power supply input 9 st(b) st non-inverting output 92 gnd signal ground 93 tt(a) txce inverting output 94 vcc power supply input 95 tt(b) txce non-inverting output 96 gnd signal ground 97 sd(a) txd inverting output 98 vcc power supply input 99 sd(b) txd non-inverting output 00 vcc power supply input
4 exar corporation 48720 kato road, fremont ca, 94538 ? (50)668-70 7 ? www.exar.com sp3508_00_072208 table . driver mode selection table 2. receiver mode selection sp3508 driver table sp3508 receiver table driver output pin v.35 mode eia-530 mode rs-232 mode (v.28) eia-530a mode rs-449 mode (v.36) x.21 mode (v.11) shutdown suggested signal mode (d0, d1, d2) 001 010 011 100 101 110 111 t 1 out(a) v.35 v.11 v.28 v.11 v.11 v.11 high-z txd(a) t 1 out(b) v.35 v.11 high-z v.11 v.11 v.11 high-z txd(b) t 2 out(a) v.35 v.11 v.28 v.11 v.11 v.11 high-z txce(a) t 2 out(b) v.35 v.11 high-z v.11 v.11 v.11 high-z txce(b) t 3 out(a) v.35 v.11 v.28 v.11 v.11 v.11 high-z txc_dce(a) t 3 out(b) v.35 v.11 high-z v.11 v.11 v.11 high-z txc_dce(b) t 4 out(a) v.28 v.11 v.28 v.11 v.11 v.11 high-z rts(a) t 4 out(b) high-z v.11 high-z v.11 v.11 v.11 high-z rts(b) t 5 out(a) v.28 v.11 v.28 v.10 v.11 v.11 high-z dtr(a) t 5 out(b) high-z v.11 high-z high-z v.11 v.11 high-z dtr(b) t 6 out(a) v.28 v.11 v.28 v.11 v.11 v.11 high-z dcd_dce(a) t 6 out(b) high-z v.11 high-z v.11 v.11 v.11 high-z dcd_dce(b) t 7 out(a) v.28 v.10 v.28 v.10 v.10 high-z high-z rl t 8 out(a) v.28 v.10 v.28 v.10 v.10 high-z high-z ll receiver input pin v.35 mode eia-530 mode rs-232 mode (v.28) eia-530a mode rs-449 mode (v.36) x.21 mode (v.11) shutdown suggested signal mode (d0, d1, d2) 001 010 011 100 101 110 111 r 1 in(a) v.35 v.11 v.28 v.11 v.11 v.11 high-z rxd(a) r 1 in(b) v.35 v.11 high-z v.11 v.11 v.11 high-z rxd(b) r 2 in(a) v.35 v.11 v.28 v.11 v.11 v.11 high-z rxc(a) r 2 in(b) v.35 v.11 high-z v.11 v.11 v.11 high-z rxc(b) r 3 in(a) v.35 v.11 v.28 v.11 v.11 v.11 high-z txc_dte(a) r 3 in(b) v.35 v.11 high-z v.11 v.11 v.11 high-z txc_dte(b) r 4 in(a) v.28 v.11 v.28 v.11 v.11 v.11 high-z cts(a) r 4 in(b) high-z v.11 high-z v.11 v.11 v.11 high-z cts(b) r 5 in(a) v.28 v.11 v.28 v.10 v.11 v.11 high-z dsr(a) r 5 in(b) high-z v.11 high-z high-z v.11 v.11 high-z dsr(b) r 6 in(a) v.28 v.11 v.28 v.11 v.11 v.11 high-z dcd_dte(a) r 6 in(b) high-z v.11 high-z v.11 v.11 v.11 high-z dcd_dte(b) r 7 in(a) v.28 v.10 v.28 v.10 v.10 high-z high-z ri r 8 in(a) v.28 v.10 v.28 v.10 v.10 high-z high-z tm
5 exar corporation 48720 kato road, fremont ca, 94538 ? (50)668-70 7 ? www.exar.com sp3508_00_072208 figure . v.28 driver output open circuit voltage figure 2. v.28 driver output loaded voltage figure 3. v.28 driver output slew rate figure 4. v.28 driver output short-circuit current figure 6. v.28 driver output rise/fall times figure 5. v.28 driver output power-off impedance test circuits a v o c c a v t c 3k a v t c 7k o s c i l l o s c o p e scope used f or sle w r ate measurement. a i s c c a c v c c = 0 v 2v i x a c 3 k 2 5 0 0 p f o s c i l l o s c o p e
6 exar corporation 48720 kato road, fremont ca, 94538 ? (50)668-70 7 ? www.exar.com sp3508_00_072208 figure 7. v.28 receiver input impedance figure 8. v.28 receiver input open circuit bias figure 9. v. 0 driver output open-circuit voltage figure 0. v. 0 driver output test terminated volt - age figure 2. v. 0 driver output power-off current figure . v.0 driver output short-circuit current a c i i a 15v a c v o c a v o c 3.9k c a v t 450 c a i s c c a c 0 . 2 5 v v c c = 0 v i x
7 exar corporation 48720 kato road, fremont ca, 94538 ? (50)668-70 7 ? www.exar.com sp3508_00_072208 figure 3. v. 0 driver output transition time figure 4. v.0 receiver input current figure 5. v.0 receiver input iv graph figure 6. v. driver output open-circuit voltage figure 7. v. driver output test terminated volt - age figure 8. v. driver output short-circuit current a 450 c o s c i l l o s c o p e a c i i a 10v a b v o c 3.9k v oca v ocb c a b v t 50 v os c 50 a b c i s a i s b v . 1 0 r e c e i v e r + 3 . 2 5 m a - 3 . 2 5 m a + 3 v + 1 0 v - 3 v - 1 0 v m a x i m u m i n p u t c u r r e n t v e r s u s v o l t a g e
8 exar corporation 48720 kato road, fremont ca, 94538 ? (50)668-70 7 ? www.exar.com sp3508_00_072208 figure 9. v. driver output power-off current figure 20. v. receiver input current figure 2 . v. driver output rise/fall time figure 22. v. receiver input iv graph a b c i xa 0 . 2 5 v a b c i xb 0 . 2 5 v v c c = 0 v v c c = 0 v a b c i ia 1 0 v c i ib 1 0 v a b a b 50 c 50 50 v e o s c i l l o s c o p e v . 1 1 r e c e i v e r + 3 . 2 5 m a - 3 . 2 5 m a + 3 v + 1 0 v - 3 v - 1 0 v m a x i m u m i n p u t c u r r e n t v e r s u s v o l t a g e
9 exar corporation 48720 kato road, fremont ca, 94538 ? (50)668-70 7 ? www.exar.com sp3508_00_072208 figure 23. v. receiver input current w/ termina - tion figure 24. v. receiver input graph with termina - tion figure 25. v.35 driver output test terminated volt - age figure 26. v.35 driver output source impedance a b c i ia 6 v c i ib 6 v a b 100 to 150 100 to 150 a b v 2 5 0 c 2 4 k h z , 5 5 0 m v p-p s i n e w a v e v 1 a b 50 c 50 v t v o s v . 1 1 r e c e i v e r w / o p t i o n a l c a b l e t e r m i n a t i o n ( 1 0 0 w t o 1 5 0 w ) i [ m a ] = v [ v ] / 0 . 1 i [ m a ] = v [ v ] - 3 ) / 4 . 0 i [ m a ] = v [ v ] / 0 . 1 i [ m a ] = v [ v ] - 3 ) / 4 . 0 - 6 v - 3 v + 3 v + 6 v m a x i m u m i n p u t c u r r e n t v e r s u s v o l t a g e figure 27. v.35 driver output short-circuit imped - ance a b c i s c 2v
20 exar corporation 48720 kato road, fremont ca, 94538 ? (50)668-70 7 ? www.exar.com sp3508_00_072208 figure 3 . driver output leakage current test figure 32. driver/receiver timing test circuit figure 29. v.35 receiver input source impedance figure 28. v.35 driver output rise/fall time figure 30. v.35 receiver input short-circuit imped - ance a b c 50 o s c i l l o s c o p e 50 50 a b v 2 50 c 2 4 k h z , 5 5 0 m v p-p s i n e w a v e v 1 a b c i s c 2v a b i z s c logic ?1? 10v 1 1 1 d 2 d 1 d 0 v cc = 0v v cc an y one of the three conditions f or disab ling the dr iv er . i z s c 10v c l 1 1 5 p f r o u t b a b a t i n c l 2 f in (50% duty cycle, 2.5v p-p )
2 exar corporation 48720 kato road, fremont ca, 94538 ? (50)668-70 7 ? www.exar.com sp3508_00_072208 figure 33. driver timing test load circuit figure 34. receiver timing test load circuit figure 35. driver propagation delays figure 36. driver enable and disable times figure 37. receiver propagation delays 5 0 0 c l o u t p u t u n d e r t e s t s 1 s 2 v c c 1 k 1 k c r l r e c e i v e r o u t p u t s 1 s 2 t e s t p o i n t v c c + 3 v 0 v 5 v v ol a , b 0 v 1 . 5 v 1 . 5 v t zl t zh v oh a , b 2 . 3 v 2 . 3 v t lz t hz 0 . 5 v 0 . 5 v o u t p u t n o r m a l l y l o w o u t p u t n o r m a l l y h i g h m x o r t x _ e n a b l e f = 1 m h z ; t r 1 0 n s ; t f 1 0 n s v oh v ol r e c e i v e r o u t ( v oh - v ol ) / 2 ( v oh - v ol ) / 2 t plh f > 1 0 m h z ; t r < 5 n s ; t f < 5 n s o u t p u t v 0d2 + v 0d2 ? a ? b 0 v 0 v t phl i n p u t t skew = | t phl - t plh | + 3 v 0 v d r i v e r i n p u t a b d r i v e r o u t p u t v o + d i f f e r e n t i a l o u t p u t v b ? v a 0 v v o ? 1 . 5 v 1 . 5 v t plh t r t f f > 1 0 m h z ; t r < 5 n s ; t f < 5 n s v o 1 / 2 v o 1 / 2 v o t phl t dplh t dphl t skew = | t dplh - t dphl |
22 exar corporation 48720 kato road, fremont ca, 94538 ? (50)668-70 7 ? www.exar.com sp3508_00_072208 figure 38. receiver enable and disable times figure 39. v.28 (rs-232) and v. 0 (rs-423) driver enable and disable times + 3 v 0 v t x _ e n a b l e 1 . 5 v 1 . 5 v t zl f = 6 0 k h z ; t r < 1 0 n s ; t f < 1 0 n s t out t lz o u t p u t l o w 0 v + 3 v 0 v v oh 1 . 5 v 1 . 5 v t zh f = 6 0 k h z ; t r < 1 0 n s ; t f < 1 0 n s t out t hz o u t p u t h i g h 0 v t x _ e n a b l e v ol 0 . 5 v v oh - v ol 0 . 5 v - v ol 0 . 5 v - + 3 v 0 v + 3 . 3 v r e c e i v e r o u t 0 v 1 . 5 v 1 . 5 v t zl t zh f = 1 m h z ; t r < 1 0 n s ; t f < 1 0 n s r e c e i v e r o u t 1 . 5 v 1 . 5 v t lz t hz 0 . 5 v 0 . 5 v o u t p u t n o r m a l l y l o w o u t p u t n o r m a l l y h i g h v il v ih d e c x r x enable
23 exar corporation 48720 kato road, fremont ca, 94538 ? (50)668-70 7 ? www.exar.com sp3508_00_072208 figure 40. typical v. 0 driver output waveform. figure 4 . typical v. driver output waveform. figure 42. typical v.28 driver output waveform. figure 43. typical v.35 driver output waveform.
24 exar corporation 48720 kato road, fremont ca, 94538 ? (50)668-70 7 ? www.exar.com sp3508_00_072208 figure 44. functional diagram txd sd(a) sd(b) sden v cc v dd c1- c1+ +3.3v (decoupling capacitor not shown) 1 m f sp3508 txce tt(a) tt(b) tten st st(a) st(b) sten rd(a) rxd rden rd(b) r t(a) rxc r ten r t(b) txc(a) txc txcen txc(b) cs(a) cts csen cs(b) dm(a) dsr dmen dm(b) rr t(a) dcd_dte rr ten rr t(b) tm(a) tm tmen rt s rs(a) rs(b) rsen dtr tr(a) tr(b) tren dcd_dce rrc(a) rrc(b) rrcen ll ll(a) llen c2- c2+ 1 m f 1 m f gnd d0 d1 d2 term-off d-la tch v .10-gnd rl rl(a) rlen ic ri icen loopba ck 76 29 50 39 10 49 52 40 11 51 55 41 12 53 57 42 14 56 59 43 13 58 62 44 15 61 63 45 16 64 46 17 18 19 20 21 22 30 +3.3v (see pinout assignments for gnd and v cc pins) 74 70 72 69 agnd 31 97 99 2 32 93 95 3 33 89 91 4 34 81 83 6 35 85 87 5 36 79 77 7 37 67 8 38 65 9 60 28 v .35 mode rx enable 51ohms 51ohms 124ohms receiver termina tion netw ork v .11 mode v .35 mode tx enable 51ohms 51ohms 124ohms v .35 driver termina tion netw ork v ss1 68 v ss2 1 m f 27 1 m f 1 m f 24 26 av cc c3- c3+ inverter regulated charge pump c vdd c1 c2 c3 c vss1 c vss2
25 exar corporation 48720 kato road, fremont ca, 94538 ? (50)668-70 7 ? www.exar.com sp3508_00_072208 the sp3508 contains highly integrated se - rial transceivers that offer programmability between interface modes through software control. the sp3508 offers the hardware interface modes for rs-232 (v.28), rs- 449/v.36 (v. and v. 0), eia-530 (v. and v. 0), eia-530a (v. and v. 0), v.35 (v.35 and v.28) and x.2 (v. ). the interface mode selection is done via three control pins, which can be latched via microprocessor control. the sp3508 has eight drivers, eight receiv - ers, and a patented on-board charge pump (5,306,954) that is ideally suited for wide area network connectivity and other multi- protocol applications. other features include digital and line loopback modes, individual enable/disable control lines for each driver and receiver, fail-safe when inputs are either open or shorted. theory of operation the sp3508 device is made up of ) the drivers 2) the receivers 3) charge pumps 4) dte/dce switching algorithm 5) control logic. drivers the sp3508 has eight enhanced indepen - dent drivers. control for the mode selection is done via a three-bit control word into d0, d , and d2. the drivers are prearranged such that for each mode of operation, the relative position and functionality of the driv - ers are set up to accommodate the selected interface mode. as the mode of the drivers is changed, the electrical characteristics will change to support the required signal levels. the mode of each driver in the dif - ferent interface modes that can be selected is shown in table . there are four basic types of driver circuits C itu-t-v.28 (rs-232), itu-t-v. 0 (rs-423), itu-t-v. (rs-422), and ccitt-v.35. the v.28 (rs-232) drivers output single- ended signals with a minimum of + 5v (with 3k & 2500pf loading), and can operate over 20kbps. since the sp3508 uses a charge pump to generate the rs-232 output rails, the driver outputs will never exceed + 0v. the v.28 driver architecture is similar to sipex's standard line of rs-232 transceivers. the rs-423 (v. 0) drivers are also single- ended signals which produce open circuit v ol and v oh measurements of + 4.0v to + 6.0v. when terminated with a 450 load to ground, the driver output will not deviate more than 0% of the open circuit value. this is in com - pliance of the itu v.10 specifcation. the v.10 (rs-423) drivers are used in rs-449/v.36, eia-530, and eia-530a modes as category ii signals from each of their corresponding specifcations. the v.10 driver can transmit over 20kbps if necessary. the third type of drivers are v. (rs-422) differential drivers. due to the nature of dif - ferential signaling, the drivers are more im - mune to noise as opposed to single-ended transmission methods. the advantage is evident over high speeds and long trans - mission lines. the strength of the driver outputs can produce differential signals that can maintain + 2v differential output levels with a load of 100. the strength allows the sp3508 differential driver to drive over long cable lengths with minimal signal degrada - tion. the v. drivers are used in rs-449, eia-530, eia-530a and v.36 modes as category i signals which are used for clock and data. exar's new driver design over its predecessors allow the sp3508 to operate over 20mbps for differential transmission. the fourth type of drivers are v.35 differential drivers. there are only three available on the sp3508 for data and clock (txd, txce, and txc in dce mode). features
26 exar corporation 48720 kato road, fremont ca, 94538 ? (50)668-70 7 ? www.exar.com sp3508_00_072208 these drivers are current sources that drive loop current through a differential pair resulting in a 550mv differential voltage at the receiver. these drivers also incorporate fxed termination networks for each driver in order to set the v oh and v ol depending on load conditions. this termination network is basically a y confguration consisting of two 51? resistors connected in series and a 124? resistor connected between the two 50? resistors to gnd. filtering can be done on these pins to reduce common mode noise transmitted over the transmission line by connecting a capacitor to ground. the drivers also have separate enable pins which simplifes half-duplex confgurations for some applications, especially program - mable dte/dce. the enable pins will either enable or disable the output of the drivers according to the appropriate active logic illustrated on figure 44. the enable pins have internal pull-up and pull-down devices, depending on the active polarity of the re - ceiver, that enable the driver upon power-on if the enable lines are left foating. during disabled conditions, the driver outputs will be at a high impedance 3-state. the driver inputs are both ttl or cmos compatible. all driver inputs have an internal pull-up resistor so that the output will be at a defned state at logic low (0). unused driver inputs can be left foating. the inter - nal pull-up resistor value is approximately 500k?. receivers the sp3508 has eight enhanced inde - pendent receivers. control for the mode selection is done via a three-bit con - trol word that is the same as the driver control word. therefore, the modes for the drivers and receivers are identical in the application. like the drivers, the receivers are prearranged for the specifc requirements of the synchronous serial interface. as the operating mode of the receivers is changed, the electrical characteristics will change to support the required serial interface protocols of the receivers. table shows the mode of each receiver in the different interface modes that can be selected. there are two basic types of receiver cir - cuitsitu-t-v .28 (rs-232) and itu-t-v. , (rs-422). the rs-232 (v.28) receiver is single-ended and accepts rs-232 signals from the rs- 232 driver. the rs-232 receiver has an operating input voltage range of + 5v and can receive signals downs to + 3v. the input sensitivity complies with rs-232 and v.28 at + 3v. the input impedance is 3k? to 7k? in accordance to rs-232 and v.28. the re - ceiver output produces a ttl/cmos signal with a +2.4v minimum for a logic and a +0.4v maximum for a logic 0. the rs-232 (v.28) protocol uses these receivers for all data, clock and control signals. they are also used in v.35 mode for control line signals: cts, dsr, ll, and rl. the rs-232 receiv - ers can operate over 20kbps. the second type of receiver is a differential type that can be confgured internally to support itu-t-v. 0 and ccitt-v.35 depending on its input conditions. this receiver has a typical input impedance of 10k? and a differential threshold of less than + 200mv, which complies with the itu-t-v.11 (rs-422) specifcations. v. receivers are used in rs-449/v.36, eia-530, eia-530a and x.2 as category i signals for receiving clock, data, and some control line signals not covered by category ii v. 0 circuits. the differential v. trans - ceiver has improved architecture that allows over 20mbps transmission rates. receivers dedicated for data and clock (rxd, rxc, txc) incorporate internal termination for v. . the termination resistor is typi - cally 120? connected between the a and b inputs. the termination is essential for minimizing crosstalk and signal refection over the transmission line . the minimum value is guaranteed to exceed 100?, thus complying with the v. and rs-422 speci - fcations. this resistor is invoked when the receiver is operating as a v. receiver, in modes eia-530, eia-530a, rs-449/v.36, and x.2. features
27 exar corporation 48720 kato road, fremont ca, 94538 ? (50)668-70 7 ? www.exar.com sp3508_00_072208 the same receivers also incorporate a ter - mination network internally for v.35 applica - tions. for v.35, the receiver input termination is a y termination consisting of two 51? resistors connected in series and a 124? resistor connected between the two 50? resistors and gnd. the receiver itself is identical to the v. receiver. the differential receivers can be confgured to be itu-t-v. 0 single-ended receivers by internally connecting the non-inverting input to ground. this is internally done by default from the decoder. the non-inverting input is rerouted to v 0gnd and can be grounded separately. the itu-t-v. 0 receivers can operate over 20kbps and are used in rs- 449/v.36, e a-530, e a-530a and x.2 modes as category ii signals as indicated by their corresponding specifcations. all receivers include an enable/disable line for disabling the receiver output allowing convenient half-duplex confgurations. the enable pins will either enable or disable the output of the receivers according to the ap - propriate active logic illustrated on figure 44. the receivers enable lines include an internal pull-up or pull-down device, depend - ing on the active polarity of the receiver, that enables the receiver upon power up if the enable lines are left foating. during disabled conditions, the receiver outputs will be at a high impedance state. if the receiver is disabled any associated termination is also disconnected from the inputs. all receivers include a fail-safe feature that outputs a logic high when the receiver inputs features are open, terminated but open, or shorted together. for single-ended v.28 and v. 0 receivers, there are internal 5k? pull-down resistors on the inputs which produces a logic high ( ) at the receiver outputs. the differential receivers have a proprietary cir - cuit that detect open or shorted inputs and if so, will produce a logic high ( ) at the receiver output. charge pump sp3508 uses an internal capacitive charge pump to generate vdd and vss. the design is a patented (5,306,954) four-phased volt - age shifting charge pump converters that converts the input voltage of 3.3v to nomi - nal output voltages of +/-6v (vdd & vss ). sp3508 also includes an inverter block that inverts vcc to -vcc (vss2). there is a free-running oscillator that controls the four phases of the voltage shifting. a description of each phase follows. 4-phased doubler pump phase 1 -v ss charge storage -during this phase of the clock cycle, the positive side of capacitors c and c2 are initially charged to v cc . c + is then switched to ground and the charge in c - is transferred to c2-. since c2+ is con - nected to v cc , the voltage potential across capacitor c2 is now 2xv cc . v cc = + 3 v ? 3 v ? 3 v + 3 v v ss1 s t o r a g e c a p a c i t o r v dd s t o r a g e c a p a c i t o r c 1 c 2 + + + + ? ? ? ? c vdd c vss1 figure 45. charge pump - phase .
28 exar corporation 48720 kato road, fremont ca, 94538 ? (50)668-70 7 ? www.exar.com sp3508_00_072208 phase 2 -v ss transfer -phase two of the clock connects the negative terminal of c2 to the v ss storage capacitor and the positive terminal of c2 to ground, and transfers the negative generated voltage to c vss . this generated voltage is regulated to -5.5v. simultaneously, the positive side of the capacitor c is switched to v cc and the negative side is connected to ground. features phase 3 -v dd charge storage -the third phase of the clock is identical to the frst phase-the charge transferred in c produces -v cc in the negative terminal of c which is applied to the negative side of the capacitor c2. since c2+ is at v cc , the voltage potential across c2 is 2xv cc . v cc = + 3 v ? 6 v v ss s t o r a g e c a p a c i t o r v dd s t o r a g e c a p a c i t o r c 1 c 2 + + + + ? ? ? ? c vdd c vss1 figure 46. charge pump - phase 2. v cc = + 3 v ? 3 v + 3 v ? 3 v v ss1 s t o r a g e c a p a c i t o r v dd s t o r a g e c a p a c i t o r c 1 c 2 + + + + ? ? ? ? c vss1 c vdd figure 47.charge pump - phase 3. -v dd transfer -the fourth phase of the clock connects the negative terminal of c2 to ground, and transfers the generated 5.5v across c2 to c vdd , the v dd storage capacitor. this voltage is regulated to +5.5v. at the regulated voltage, the internal oscillator is disabled and simulta - neously with this, the positive side of capacitor c is switched to v cc and the negative side is connected to ground, and the cycle begins again. the charge pump cycle will continue as long as the operational conditions for the internal oscillator are present. since both v+ and v- are separately generated from v cc ; in a no-load condition v+ and v- will be symmetrical. older charge pump approaches that generate v- from v+ will show a decrease in the mag - nitude of v- compared to v+ due to the inherent ineffciencies in the design. the clock rate for the charge pump typically operates at 250khz. the external capacitors can be as low as f with a 6v breakdown voltage rating. phase 4
29 exar corporation 48720 kato road, fremont ca, 94538 ? (50)668-70 7 ? www.exar.com sp3508_00_072208 v cc = + 3 v + 6 v v ss1 s t o r a g e c a p a c i t o r v dd s t o r a g e c a p a c i t o r c 1 c 2 + + + + ? ? ? ? c vdd c vss1 figure 48. charge pump - phase 4. 2-phased inverter pump phase 1 please refer to fgure below: in the frst phase of the clock cycle, switches s2 and s4 are opened and s1 and s3 closed. this connects the fying capacitor, c3, from vin to ground. c3 charge up to the input voltage applied at vcc. phase 2 in the second phase of the clock cycle, switches s2 and s4 are closed and s and s3 are opened. this connects the fying capacitor, c3, in parallel with the output capacitor, c vss2 . the charge stored in c3 is now transferred to c vss2 . simultaneously, the negative side of c vss2 is connected to v ss 2 and the positive side is connected to ground. with the voltage across c vss2 smaller than the voltage across c3, the charge fows from c3 to c vss2 until the voltage at the v ss 2 equals -v cc . c 3 s 2 s 1 s 3 s 4 v ss2 c vss2 + + v cc v ss2 = - v cc figure 49. circuit for an ideal voltage inverter. features
30 exar corporation 48720 kato road, fremont ca, 94538 ? (50)668-70 7 ? www.exar.com sp3508_00_072208 recommended signals and port pin assignments pin number pin mnemonic circuit pin mnemonic pin number signal type mnemo nic db-25 pin(f) signal type mnemo nic db-25 pin(f) signal type mnemo nic db-37 pin(f) signal type mnemo nic m34 pin(f) signal type mnemo nic db-15 pin(f) 31 txd sd(a) 97 v.28 bb 3 v.11 bb(a) 3 v.11 rd(a) 6 v.35 104 r v.11 r(a) 4 2 sden sd(b) 99 v.11 bb(b) 16 v.11 rd(b) 24 v.35 104 t v.11 r(b) 11 32 txce tt(a) 93 v.28 dd 17 v.11 dd(a) 17 v.11 rt(a) 8 v.35 115 v v.11 b(a) 7** 3 tten tt(b) 95 v.11 dd(b) 9 v.11 rt(b) 26 v.35 115 x v.11 b(b) 14** 33 st st(a) 89 v.28 db 15 v.11 db(a) 15 v.11 st(a) 5 v.35 114 y v.11 s(a) 6 4 sten st(b) 91 v.11 db(b) 12 v.11 st(b) 23 v.35 114 aa v.11 s(b) 13 34 rts rs(a) 81 v.28 cb 5 v.11 cb(a) 5 v.11 cs(a) 9 v.28 106 d v.11 i(a) 5 5 rsen rs(b) 83 v.11 cb(b) 13 v.11 cs(b) 27 v.11 i(b) 12 35 dtr tr(a) 85 v.28 cc 6 v.11 cc(a) 6 v.11 dm(a) 11 v.28 107 e 6 tren tr(b) 87 v.11 cc(b) 22 v.11 dm(b) 29 36 dcd_dce rrc(a) 79 v.28 cf 8 v.11 cf(a) 8 v.11 rr(a) 13 v.28 109 f 7 rrcen rrc(b) 77 v.11 cf(b) 10 v.11 rr(b) 31 37 rl rl(a) 67 v.28 ce 22 v.28 125 j 8 rlen 38 ll ll(a) 65 v.28 tm 25 v.10 tm 25 v.10 tm 18 v.28 142 nn 9 llen# 39 rxd rd(a) 50 v.28 ba 2 v.11 ba(a) 2 v.11 sd(a) 4 v.35 103 p v.11 t(a) 2 10 rden# rd(b) 49 v.11 ba(b) 12 v.11 sd(b) 22 v.35 103 s v.11 t(b) 9 40 rxc rt(a) 52 v.28 da 24 v.11 da(a) 24 v.11 tt(a) 17 v.35 113 u v.11 x(a) 7** 11 rten# rt(b) 51 v.11 da(b) 11 v.11 tt(b) 35 v.35 113 w v.11 x(b) 14** 41 txc txc(a) 55 12 txcen# txc(b) 53 42 cts cs(a) 57 v.28 ca 4 v.11 ca(a) 4 v.11 rs(a) 7 v.28 105 c v.11 c(a) 3 13 csen# cs(b) 56 v.11 ca(b) 19 v.11 rs(b) 25 v.11 c(b) 10 43 dsr dm(a) 59 v.28 cd 20 v.11 cd(a) 20 v.11 tr(a) 12 v.28 108 h 14 dmen# dm(b) 58 v.11 cd(b) 23 v.11 tr(b) 30 44 dcd_dte rrt(a) 62 15 rrten# rrt(b) 61 45 ri ic 63 v.28 rl 21 v.10 rl 21 v.10 rl 14 v.28 140 n 16 icen# 46 tm tm(a) 64 v.28 ll 18 v.10 ll 18 v.10 ll 10 v.28 141 l 17 tmen sp3508 multiprotocol configured as dce interface to system logic interface to port- connector receiver_4 receiver_5 receiver_6 driver_7 driver_8 rs-449 v.35 x.21 driver_1 rs-232 or v.24 eia-530 receiver_2 receiver_3 driver_2 driver_3 driver_4 driver_5 receiver_1 driver_6 spare drivers and receivers may be used for optional signals (signal quality, rate detect, standby) or may be disabled using individual enable pins for each driver and receiver ** x.21 use either b() or x(), not both pin assignments and signal functions are subject to national or regional variation and proprietary / non-standard implementations receiver_7 receiver_8 dce c onfiguration
3 exar corporation 48720 kato road, fremont ca, 94538 ? (50)668-70 7 ? www.exar.com sp3508_00_072208 recommended signals and port pin assignments pin number pin mnemonic circuit pin mnemonic pin number signal type mnemo nic db-25 pin(m) signal type mnemo nic db-25 pin(m) signal type mnemo nic db-37 pin(m) signal type mnemo nic m34 pin(m) signal type mnemo nic db-15 pin(m) 31 txd sd(a) 97 v.28 ba 2 v.11 ba(a) 2 v.11 sd(a) 4 v.35 103 p v.11 t(a) 2 2 sden sd(b) 99 v.11 ba(b) 12 v.11 sd(b) 22 v.35 103 s v.11 t(b) 9 32 txce tt(a) 93 v.28 da 24 v.11 da(a) 24 v.11 tt(a) 17 v.35 113 u v.11 x(a) 7** 3 tten tt(b) 95 v.11 da(b) 11 v.11 tt(b) 35 v.35 113 w v.11 x(b) 14** 33 st st(a) 89 4 sten st(b) 91 34 rts rs(a) 81 v.28 ca 4 v.11 ca(a) 4 v.11 rs(a) 7 v.28 105 c v.11 c(a) 3 5 rsen rs(b) 83 v.11 ca(b) 19 v.11 rs(b) 25 v.11 c(b) 10 35 dtr tr(a) 85 v.28 cd 20 v.11 cd(a) 20 v.11 tr(a) 12 v.28 108 h 6 tren tr(b) 87 v.11 cd(b) 23 v.11 tr(b) 30 36 dcd_dce rrc(a) 79 7 rrcen rrc(b) 77 37 rl rl(a) 67 v.28 rl 21 v.10 rl 21 v.10 rl 14 v.28 140 n 8 rlen 38 ll ll(a) 65 v.28 ll 18 v.10 ll 18 v.10 ll 10 v.28 141 l 9 llen# 39 rxd rd(a) 50 v.28 bb 3 v.11 bb(a) 3 v.11 rd(a) 6 v.35 104 r v.11 r(a) 4 10 rden# rd(b) 49 v.11 bb(b) 16 v.11 rd(b) 24 v.35 104 t v.11 r(b) 11 40 rxc rt(a) 52 v.28 dd 17 v.11 dd(a) 17 v.11 rt(a) 8 v.35 115 v v.11 b(a) 7** 11 rten# rt(b) 51 v.11 dd(b) 9 v.11 rt(b) 26 v.35 115 x v.11 b(b) 14** 41 txc txc(a) 55 v.28 db 15 v.11 db(a) 15 v.11 st(a) 5 v.35 114 y v.11 s(a) 6 12 txcen# txc(b) 53 v.11 db(b) 12 v.11 st(b) 23 v.35 114 aa v.11 s(b) 13 42 cts cs(a) 57 v.28 cb 5 v.11 cb(a) 5 v.11 cs(a) 9 v.28 106 d v.11 i(a) 5 13 csen# cs(b) 56 v.11 cb(b) 13 v.11 cs(b) 27 v.11 i(b) 12 43 dsr dm(a) 59 v.28 cc 6 v.11 cc(a) 6 v.11 dm(a) 11 v.28 107 e 14 dmen# dm(b) 58 v.11 cc(b) 22 v.11 dm(b) 29 44 dcd_dte rrt(a) 62 v.28 cf 8 v.11 cf(a) 8 v.11 rr(a) 13 v.28 109 f 15 rrten# rrt(b) 61 v.11 cf(b) 10 v.11 rr(b) 31 45 ri ic 63 v.28 ce 22 v.28 125 j 16 icen# 46 tm tm(a) 64 v.28 tm 25 v.10 tm 25 v.10 tm 18 v.28 142 nn 17 tmen rs-449 v.35 x.21 receiver_7 receiver_8 rs-232 or v.24 eia-530 receiver_4 receiver_5 receiver_6 driver_7 driver_8 driver_6 driver_2 driver_3 driver_4 driver_5 spare drivers and receivers may be used for optional signals (signal quality, rate detect, standby) or may be disabled using individual enable pins for each driver and receiver ** x.21 use either b() or x(), not both pin assignments and signal functions are subject to national or regional variation and proprietary / non-standard implementations sp3508 multiprotocol configured as dte interface to system logic interface to port- connector driver_1 receiver_1 receiver_2 receiver_3 dte c onfiguration
32 exar corporation 48720 kato road, fremont ca, 94538 ? (50)668-70 7 ? www.exar.com sp3508_00_072208 term_off function the sp3508 contains a term_off pin that disables all three receiver input termination networks regardless of mode. this allows the device to be used in monitor mode ap - plications typically found in networking test equipment. the term_off pin internally contains a pull-down device with an impedance of over 500k, which will default in a "on" condition during power-up if v.35 receivers enable line and the shutdown mode from the decoder will disable the termination regard - less of term_off. loopback function the sp3508 contains a loopback pin that invokes a loopback path. this loopback path is illustrated in figure 50. loopback has an internal pull-up resistor that defaults to normal mode during power up or if the pin is left foating. during loopback, the driver out - put and receiver input characteristics will still adhere to its appropriate specifcations. decoder and d_latch function the sp3508 contains a d_latch pin that latches the data into the d0, d and d2 decoder inputs. if tied to a logic low ("0"), the latch is transparent, allowing the data at the decoder inputs to propagate through and program the sp3508 accordingly. if tied to a logic high ("1"), the latch locks out the data and prevents the mode from changing until this pin is brought to a logic low. features there are internal pull-up devices on d0, d and d2, which allow the device to be in shutdown mode ("111") upon power up. however, if the device is powered-up with the d_latch at a logic high, the decoder state of the sp3508 will be undefned. ctr1/ctr2 european compliancy as with all of exar's previous multi-protocol serial transceiver ic's the drivers and re - ceivers have been designed to meet all the requirements to net /net2 and tbr2 in order to meet ctr /ctr2 compliancy. the sp3508 is also tested in-house at exar and adheres to all the net /2 physical layer testing and the itu series v specifcations before shipment. please note that although the sp3508, as with its predecessors, ad - here to crt /ctr2 compliancy testing, any complex or usual confguration should be double-checked to ensure ctr /ctr2 compliance. consult the factory for details.
33 exar corporation 48720 kato road, fremont ca, 94538 ? (50)668-70 7 ? www.exar.com sp3508_00_072208 figure 50. loopback path sd(a) sd(b) rd(a) rd(b) tt(a) tt(b) r t(a) r t(b) txd rxd txce rxc st(a) st(b) txc(a) txc(b) st txc rs(a) rs(b) cs(a) cs(b) tr(a) tr(b) dm(a) dm(b) r ts cts dtr dsr rrc(a) rrc(b) rr t(a) rr t(b) dcd_dce dcd_dte rl(a) ic rl ri ll(a) tm(a) ll tm 31 39 32 40 33 41 34 42 35 43 36 44 37 45 38 46 97 99 50 49 93 95 52 51 89 91 55 53 81 83 57 56 85 87 59 58 79 77 62 61 67 63 65 64
34 exar corporation 48720 kato road, fremont ca, 94538 ? (50)668-70 7 ? www.exar.com sp3508_00_072208 figure 51. sp3508 typical operating confguration to serial port connector with dce/dte program - mability 20 (v .11, v .28) dtr_dsr_a 23 (v .11) dtr_dsr_b 1 m f 1 m f c vdd v cc v dd c1- c2- c1+ c2+ 1 m f sp3508cf txd txce st rt s dtr dcd_dce rl rxc txc cts dsr dcd_dte ri tm 10 m f m db-26 serial po rt connector pins signal (dte_dce) 2 (v .11, v .35, v .28) txd_rxd_a 14 (v .11, v .35) txd_rxd_b 11 (v .11, v .35) txce_txc_b 25 (v .10, v .28) ll_tm 15 (v .11, v .35, v .28) *txc_rxc_a 12 (v .11, v .35) *txc_rxc_b sden 24 (v .11, v .35, v .28) txce_txc_a 3 (v .11, v .35, v .28) rxd_txd_a 16 (v .11, v .35) rxd_txd_b 8 (v .11, v .28) dcd_dcd_a 10 (v .11) dcd_dcd_b 9 (v .11, v .35) rxc_txce_b 17 (v .11, v .35, v .28) rxc_txce_a llen sten gnd * - dr iv er applies f or dce only on pins 15 and 12. receiv er applies f or dte only on pins 15 and 12. +3.3v i/o lines represented by doub le arrowhead signifies a bi-directional bu s. input line output line ll rxd tten rsen tren rrcen rlen rden tmen txcen r ten csen dmen rr ten icen term_off d_la tch d0 d1 d2 charge pump sectio n tr ansceiv er sectio n logic sectio n +3.3v 21 (v .10, v .28) rl_ri 22 (v .10, v .28) ri_rl 18 (v .10, v .28) ll_tm dce/dte dr iv er applies f or dce only on pins 8 and 10. receiv er applies f or dte only on pins 8 and 10. loopba ck +3.3v 19 (v .11) r ts_cts_b 4 (v .11, v .28) r ts_cts_a 6 (v .11, v .28) dsr_dtr_a 22 (v .11) dsr_dtr_b 13 (v .11) cts_r ts_b 5 (v .11, v .28) cts_r ts_a 31 sd(a) 35 34 38 39 40 42 43 44 41 32 36 45 37 46 agnd sd(b) tt(a) tt(b) st(a) st(b) rs(a) rs(b) tr(a) tr(b) rrc(a) rrc(b) rl(a) rd(a) ll(a) rd(b) r t(a) r t(b) txc(a) txc(b) cs(a) cs(b) dm(a) dm(b) rr t(a) rr t(b) ic tm(a) 18 19 20 97 99 93 95 89 91 81 83 85 87 79 77 67 50 65 49 51 55 53 57 56 59 58 62 61 63 64 52 21 22 30 28 +3.3v av cc 24 26 68 27 v ss2 v ss1 c3+ c3- 69 72 70 74 76 29 1 m f c1 c2 c3 c vss1 c vss2 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 33
35 exar corporation 48720 kato road, fremont ca, 94538 ? (50)668-70 7 ? www.exar.com sp3508_00_072208 package: 100 p in lqfp
36 exar corporation 48720 kato road, fremont ca, 94538 ? (50)668-70 7 ? www.exar.com sp3508_00_072208 ordering information part number temperature range package types SP3508CF-L ........................................... 0c to +70c .................................................. 00Cpin jedec lqfp sp3508ef-l ........................................ -40c to +85c .................................................. 00Cpin jedec lqfp notice exar corporation reserves the right to make changes to any products contained in this publication in order to improve design, performance or reliabil - ity. exar corporation assumes no representation that the circuits are free of patent infringement. charts and schedules contained herein are only for illustration purposes and may vary depending upon a user's specifc application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to signifcantly af fect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writting, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized ; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2008 exar corporation datasheet july 2008 send your interface technical inquiry with technical details to: uarttechsupport@exar.com reproduction, in part or whole, without the prior written consent of exar corporation is prohibited. date revision description /2/04 a implemented tracking revision 2/27/04 b included diamond column in spec table inidcating which specs apply over full operating temperature range. correct typo to fig. 5 pin 6 and 62. 3/3/04 c corrected max dimension for symbol c on lqfp package outline 6/03/04 d added table to page 27 and 28 0/2/04 e certifed conformance to net1/net2 and tbr-1/tbr-2 tuv by tuv rhein - land (test report # tbr2/3045 940.00/04) 0/29/04 f corrected v.28 driver open circuit values, pages 27 and 28 -- both for dce and dte that ba(b) should connect to pin 4. 7/7/08 .0.0 change revision format from letter code to number code. change logo, footnote and notice statement from sipex to exar. add t j limits to absolute maximum ratings. change propagation delay limit specifcation for v .11 and v.35 driver/receiver from 60ns maximum to 85ns maximum. update ordering information to show only rohs packaging (-l) is available. revision history

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